Panel

Moderator: David Mountain

Department of Defense

Where Is HPC Headed?

The future of high performance computing is uncertain, with a number of forces causing changes to the ecosystem. These include the slowing and end of CMOS scaling, the rise of Big Data and machine learning applications, and the increasing heterogeneity in HPC architectures. This panel will explore these challenges and provide insight into how future HPC will cope with (or take advantage of) these trends.

Panelists

Bill Harrod, IARPA

 

Bruce Jacob, University of Maryland

Bruce Jacob is a Keystone Professor of Electrical and Computer Engineering and former Director of Computer Engineering at the University of Maryland in College Park. He received the AB degree in mathematics from Harvard University in 1988 and the MS and PhD degrees in CSE from the University of Michigan in Ann Arbor in 1995 and 1997, respectively. He holds several patents in the design of circuits for electric guitars and started a company around them. He also worked for two successful startup companies in the Boston area: Boston Technology and Priority Call Management. At Priority Call Management he was the initial system architect and chief engineer. He is a recipient of a US National Science Foundation CAREER award for his work on DRAM, and he is the lead author of an absurdly large book on the topic of memory systems. His research interests include system architectures, memory systems, operating systems, and electric guitars.

 

 

Irene Qualters, NSF

In her current NSF role as Senior Science Advisor in the National Science Foundation (NSF)’s Computer and Information Science and Engineering Directorate (CISE), Irene contributes to strategic leadership and stewardship of new directions particularly in alignment with the National Science Foundation’s (NSF’s) 10 Big Ideas for Future Investment; expanded efforts in Major Research Equipment and Facilities Construction (MREFC) and Midscale Infrastructure; and help to sustain the Nation’s leadership in advanced computing through interagency and public-private partnerships,  as articulated in the National Strategic Computing Initiative (NSCI).

Prior to joining NSF, Irene had a distinguished 30-year career in industry, serving in a number of executive leadership positions in research and development organizations in the technology and biotechnology sectors. For example, she spent 20 years at Cray Research across a range of critical leadership roles; and she served for six years as Vice President at Merck Research Labs (MRL), leading Research Information Systems for MRL’s 12,000 researchers worldwide.

 

Trung Tran, former DARPA program manager

Mr. Trung Tran is a former DARPA as a program manager in the Microsystems Technology Office in October 2015- August 2017. Tran earned a BSEE from the US Air Force Academy and an MBA from Wharton- UPENN. While in the Air Force, he was stationed at Fort Meade and Hanscom AFB working under AIA. He developed cryptographic chips and command and control networks which focused on reducing time between sensor and shooter. He received 4 medals for his work in these areas. He has spent the last 15 years in silicon valley developing products which range from 100G Top of the Rack Switches, 1U Server Blades, and semiconductors including FPGAs, Memory, PHYs, and Framers. He is a former Vice Chairman of the JEDEC Board of Directors where he worked on the development of DDR3 and FBDIMM specifications. His interest included machine learning, data analytics, and non-conventional computer architecture. ​